This application claims priority under 35 USC xc2xa7119 to Japanese Patent Application No. 2000-294287 filed on Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention generally relates to an electrical power source apparatus for use in a small instrument such as a mobile phone, and in particular to a CMOS (Complementary Metal Oxide Semiconductor) inclusion reference voltage generation circuit used alone or built in another semiconductor apparatus, a method for adjusting its output value, and an electrical power source that applies such a reference voltage generation circuit.
A reference voltage generation circuit that employs a depletion type MOS transistor whose gate is connected to a source as a constant current source has been known as described for example in Japanese Patent Application Laid Open No. 04-65546. In such a description, as demonstrated in FIG. 9, a constant current characteristic is utilized while connecting the gate to the source in a depletion type MOS transistor Q1. In addition, a plurality of enhancement type MOS transistors Q12 and Q13, each having a gate and a drain connected to each other, is serially connected to be driven by the constant current. Then, voltages generated in these MOS transistors Q12 and Q13 can be taken out as reference voltages. Any one of such MOS transistors Q1, Q12, and Q13 are of an n-channel type. Voltages (Vgs) between the gate and source of the MOS transistors Q12 and Q13 are V012 and V013, respectively. Only one or two or more MOS transistors Q12 and Q13 can be employed as demonstrated in FIG. 9.
In such a circuit, the threshold voltages of respective enhancement type MOS transistors Q12 and Q13 are differentiated from each other. However, as a manner of differentiating threshold voltages among the depletion type MOS transistor Q1 and the enhancement between the MOS transistor Q12 and/or Q13, it is described that impurity density of either a base plate or a channel is changed as an example. Such a manner is performed by changing an infusion value when an ion is infused.
Another reference voltage generation circuit that promises a depletion type MOS transistor whose gate is connected to a constant current source is demonstrated in FIG. 10. The legend Q1 indicates a depletion type MOS transistor that is the same as described in FIG. 9. The legend Q2 indicates an enhancement type MOS transistor whose threshold voltage is lower (i.e., threshold voltage Vth(low)). The legend Q3 indicates an enhancement type MOS transistor whose threshold voltage is higher (i.e., threshold voltage Vth(high)). As a reference voltage (VREF), a difference between threshold voltages of respective enhancement type MOS transistors Q2 and Q3 is output.
FIG. 11 demonstrates a plurality of relations between the (Vgs) and the (Ids)xc2xd of the MOS transistors Q1, Q2, and Q3 of the reference voltage generation circuit illustrated in FIG. 10 using signals under a condition that a drain voltage is saturated. In the above, it is premised that all of conductance factors (K) of the respective MOS transistors Q1, Q2, and Q3, are the same and the legend xe2x80x9cVgsxe2x80x9d represents a voltage between a gate and a source. In addition, the legend xe2x80x9cIdsxe2x80x9d represents a drain current.
Since the Vgs of the MOS transistors Q1 is fixed to zero volts, a constant current xe2x80x9cIconstxe2x80x9d is carried in accordance with the legend Q1 of FIG. 11. Accordingly, respective xe2x80x9cVgsxe2x80x9d of the MOS transistors Q2 and Q3 wherein the Ids becomes the Iconst (Ids=Iconst) amount to V02 and V03. Since the reference voltage VREF is represented by this difference, the following formulas are established:
VREF=V03xe2x88x92V02=Vth(high)xe2x88x92Vth(low)
Accordingly, it can be understood therefrom that the reference voltage VREF can be represented by the difference between threshold voltages Vth(high) and Vth(low) of the pair of the MOS transistors Q2 and Q3.
A reference voltage VREF formed by such a circuit configuration has the following advantages. Since the reference voltage is determined by a difference between threshold voltages Vth, unevenness of the reference voltage VREF is smaller than a change in a constant current caused by unevenness of threshold voltage Vth of the depletion type MOS transistor. Second, since temperature characteristics of the MOS transistors Q2 and Q3 are substantially the same, sensitivity of the reference voltage VREF to temperature is small. Third, when comparing with a band gap reference circuit, since at least three MOS transistors are enough to constitute a reference voltage generation circuit, the reference voltage generation circuit can readily be configured within a relatively small area. The band gap reference circuit is a device that takes out a reference voltage VREF having an extraordinary small temperature coefficient by utilizing a difference in polarity of temperature performance between a voltage (Vbe: a voltage between a base and an emitter) of a PN connection type and a thermal voltage Vt. The thermal voltage Vt should be obtained by dividing KT into (q) (i.e., kT/q), wherein (k) represents a Boltzman constant, (T) represents an absolute temperature, and (q) represents a unit of electricity.
However, even by the circuit configuration of FIG. 10, there exists the following problems when achieving a reference voltage VREF having higher precision. First, since ion infusion determines respective threshold voltages Vth of MOS transistors Q2 and Q3, these unevenness are independent from each other, and the difference therebetween becomes larger. As a result, unevenness of the reference voltage VREF becomes larger. FIG. 12 demonstrates an example when the threshold Vth of the MOS transistor Q2 becomes low and that of the MOS transistor Q3 becomes high, wherein each of dotted lines represents a status before a change.
Second, since respective channel impurity profiles are different from each other, respective threshold voltages Vth and temperature performances of mobility are different from each other in a strict sense. As a result, there is a limit on improvement in a temperature performance of the reference voltage VREF. FIG. 13 demonstrates another example when temperature is high and the threshold voltages Vth and the mobilities of the MOS transistors Q2 and Q3 are changed. The dotted line therein represents a condition before a change. As noted therefrom, inclination varies.
Third, when describing a conventional process of a semiconductor apparatus provided with a reference voltage generation circuit with reference to FIG. 14, a well is formed on a wafer (in step S22) after that wafer is set (in step S21), and an element separation coat is then formed on the wafer surface (in step S23). Some ions are infused in an element area so as to determine a threshold voltage Vth, thereby a reference voltage VREF is determined (in step S24). After forming a gate electrode on the surface of the wafer (in step S25), and the source and drain on the element area (in step S26), an insulating coat (e.g. a polysilicon-metal insulating coat) is formed between a poly-silicon and a metal wiring (in step S27). Then, one or more contact holes are formed on the poly-metal insulating coat (in step S28). After forming a metal wiring on the polysilicon-metal insulating coat (in step S29), a passivation coat is formed (in step S30). A wafer test is then performed (in step S31), and a package is sealed, thereby a semiconductor apparatus is completed (in step S32).
However, in such a conventional reference voltage generation circuit, since the reference voltage VREF is determined by the threshold voltage Vth, when an ion infusion process that determines the threshold voltage Vth (refer to FIG. 14 and step S4) is over, the reference voltage VREF can not be changed. In addition, since such an ion infusion process is performed in the first half section of a manufacturing process of the semiconductor apparatus, a lot of time elapses from determination of the reference voltage VREF (i.e., specification determination) to completion of the semiconductor apparatus.
Accordingly, an object of the present invention is to address and resolve the above and other problems and provide a new reference voltage generation circuit. The above and other objects are achieved according to the present invention by providing a novel reference voltage generation circuit, that includes a depletion type MOS transistor configured to include a gate connected to a source and to function as a constant current source. At least two enhancement type MOS transistors may serially be connected to the depletion type MOS transistor and have different threshold voltages as well as substantially the same profiles of channel impurities. A pair of a floating gate and a control gate is provided in at least one of two enhancement type MOS transistors. One of the threshold voltages is determined by a difference in a coupling coefficient calculated from an area ratio of the floating gate and control gate to a channel of the enhancement type MOS transistors. In addition, one of the floating gate and control gate of the enhancement type MOS transistors includes at least one fuse circuit at an optional portion other than a channel region.
In another embodiment, the control gate includes a plurality of fuse circuits serially arranged.
In yet another embodiment, the control gate includes a plurality of fuse circuits arrange in parallel.
In yet another embodiment, at least one fuse circuit is arranged at a laminate portion of the floating gate and the control gate.
In yet another embodiment, at least one fuse circuit is arranged at a portion of the control gate, where the floating gate is not laminated.
In yet another embodiment, at least one fuse circuit is arranged at a portion of the floating gate, where the control gate is not laminated.
In yet another embodiment, an electrical power source apparatus includes a detection circuit configured to compare an electrical power source voltage with a reference voltage so as to display and control the electrical power source voltage. The reference voltage is set by the reference voltage generation circuit.